Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5077077072, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-45814-26689.so 0.77 stp x29, x30, [sp, #-16]! mov x29, sp 1.31 ldr x0, [x0, #8] 0.58 ↓ cbz x0, 130 0.30 add x1, x0, #0x10 0.56 ldr w0, [x0, #8] 18: mov x2, #0x2d18 // #11544 0.41 movk x2, #0x6100, lsl #16 0.56 movk x2, #0xf17a, lsl #32 0.77 ldr x2, [x2] asr w3, w0, #0 0.56 add x2, x2, #0x8 0.51 mov x4, x1 0.71 cmp w3, #0x8 ↓ b.lt 13c 0.58 ldr q16, [x2] 0.66 cmp w3, #0x10 ↓ b.le 94 0.75 sub w0, w3, #0x10 mov w2, w0 0.43 add x0, x1, x2 movi v17.16b, #0xf 0.75 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 nop 2.85 60: ldr q19, [x4] 2.29 and v20.16b, v19.16b, v17.16b 0.02 tbl v20.16b, {v16.16b}, v20.16b 2.61 sshr v19.16b, v19.16b, #4 0.58 tbl v19.16b, {v18.16b}, v19.16b 2.25 and v19.16b, v20.16b, v19.16b 0.79 umaxp v20.4s, v19.4s, v19.4s 1.54 mov x2, v20.d[0] 2.35 cmp x2, #0x0 ↓ b.ne 190 2.44 add x4, x4, #0x10 2.48 cmp x4, x0 ↑ b.cc 60 0.62 94: sub w0, w3, #0x8 mov w0, w0 0.43 add x0, x1, x0 0.71 cmp x4, x0 0.77 csel x4, x0, x4, hi // hi = pmore 0.60 ldr x2, [x4] 0.64 mov v17.d[0], x2 0.75 ldr x2, [x0] 0.90 mov v17.d[1], x2 0.81 movi v18.16b, #0xf 0.66 and v18.16b, v17.16b, v18.16b 0.60 tbl v16.16b, {v16.16b}, v18.16b 0.53 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 1.01 sshr v17.16b, v17.16b, #4 0.47 tbl v17.16b, {v18.16b}, v17.16b 0.21 and v16.16b, v16.16b, v17.16b 0.64 umaxp v17.4s, v16.4s, v16.4s mov x2, v17.d[0] 0.88 cmp x2, #0x0 ↓ b.eq 188 1.95 cmeq v16.16b, v16.16b, #0 movi v17.16b, #0x80 0.53 and v16.16b, v16.16b, v17.16b 0.83 ldr q17, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 1.01 ushl v16.16b, v16.16b, v17.16b uxtl2 v17.8h, v16.16b 0.77 shl v17.8h, v17.8h, #8 0.53 uaddw v16.8h, v17.8h, v16.8b 0.51 addv h16, v16.8h 0.77 umov w2, v16.h[0] mvn w2, w2 0.58 rbit w2, w2 clz w2, w2 0.62 cmp w2, #0x8 ↓ b.ge 1d0 49.65 120: sub x1, x4, x1 add w0, w1, w2 0.62 128: ldp x29, x30, [sp], #16 ← ret 130: mov x1, xzr mov w0, wzr ↑ b 18 13c: mov w0, w0 add x0, x1, x0 cmp x1, x0 ↓ b.eq 188 14c: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 180 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 14c ↓ b 188 180: sub x0, x4, x1 ↑ b 128 188: mov w0, #0xffffffff // #-1 ↑ b 128 190: cmeq v17.16b, v19.16b, #0 movi v16.16b, #0x80 and v18.16b, v17.16b, v16.16b ldr q16, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 ushl v16.16b, v18.16b, v16.16b uxtl2 v17.8h, v16.16b shl v17.8h, v17.8h, #8 uaddw v16.8h, v17.8h, v16.8b addv h16, v16.8h umov w0, v16.h[0] mvn w0, w0 rbit w0, w0 clz w0, w0 sub x1, x4, x1 add w0, w0, w1 ↑ b 128 1d0: mov x4, x0 sub w2, w2, #0x8 ↑ b 120 Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5077077072, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-45814-25497.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 1.20 24: ldp x1, x22, [x19, #56] 1.20 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 0.80 → blr x1 0.80 stlur w0, [x22, #56] 1.20 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 1.20 ldr x1, [x19, #56] 1.20 ldr x0, [x1, #8] 0.40 ldr x1, [x1, #24] 1.20 → blr x1 2.01 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 1.20 add x22, x0, #0x38 1.61 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 1.20 ldr x1, [x1, #24] 2.01 → blr x1 2.81 stlr w0, [x22] 0.80 ldr x0, [x19, #64] 1.61 add x22, x0, #0x38 1.20 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 0.40 ldr x1, [x1, #24] 0.40 → blr x1 1.20 stlr w0, [x22] 0.80 ldr x0, [x19, #64] 0.40 add x22, x0, #0x38 0.40 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 0.40 ldr x1, [x1, #24] 0.80 → blr x1 2.01 stlr w0, [x22] ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 1.61 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] → blr x1 0.80 stlr w0, [x22] 0.80 ldr x0, [x19, #64] 0.40 add x22, x0, #0x38 0.40 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 2.01 ldr x1, [x1, #24] 0.40 → blr x1 1.61 stlr w0, [x22] 1.20 ldr x0, [x19, #64] add x22, x0, #0x38 1.20 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 1.61 ldr x1, [x1, #24] 0.40 → blr x1 1.20 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 1.20 ldr x1, [x19, #56] ldr x0, [x1, #8] ldr x1, [x1, #24] 0.40 → blr x1 0.80 stlr w0, [x22] 1.20 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 0.40 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 0.40 → blr x1 1.61 stlr w0, [x22] 0.80 ldr x0, [x19, #64] 1.20 add x22, x0, #0x38 1.20 ldr x1, [x19, #56] 0.40 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 1.20 → blr x1 2.01 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 0.40 add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 1.61 ldr x0, [x1, #8] 1.20 ldr x1, [x1, #24] 0.40 → blr x1 1.61 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 0.40 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 1.20 ldr x1, [x1, #24] 1.20 → blr x1 2.01 stlr w0, [x22] 1.20 ldr x0, [x19, #64] 0.40 add x22, x0, #0x38 0.40 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.40 ldr x1, [x1, #24] 1.20 → blr x1 1.61 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 0.40 add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 1.20 ldr x0, [x1, #8] 2.01 ldr x1, [x1, #24] 0.40 → blr x1 2.41 stlr w0, [x22] 0.40 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 2.01 ldr x0, [x1, #8] 0.40 ldr x1, [x1, #24] 0.80 → blr x1 0.40 stlr w0, [x22] add x21, x21, #0x1 0.40 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret