Samples: 4K of event 'cpu-clock', 999 Hz, Event count (approx.): 5002001997, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-45752-26744.so 0.81 stp x29, x30, [sp, #-16]! mov x29, sp 1.16 ldr x0, [x0, #8] 0.56 ↓ cbz x0, 128 0.51 add x1, x0, #0x10 0.81 ldr w0, [x0, #8] 18: mov x2, #0x2d18 // #11544 0.79 movk x2, #0xe500, lsl #16 0.79 movk x2, #0xe830, lsl #32 0.84 ldr x2, [x2] asr w3, w0, #0 0.73 add x2, x2, #0x8 0.04 mov x4, x1 0.73 cmp w3, #0x8 ↓ b.lt 134 0.49 ldr q16, [x2] 0.62 cmp w3, #0x10 ↓ b.le 94 0.51 sub w0, w3, #0x10 0.51 mov w2, w0 0.02 add x0, x1, x2 0.54 movi v17.16b, #0xf 0.75 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1d0 nop 3.45 60: ldr q19, [x4] 2.40 and v20.16b, v19.16b, v17.16b 0.62 tbl v20.16b, {v16.16b}, v20.16b 2.27 sshr v19.16b, v19.16b, #4 1.01 tbl v19.16b, {v18.16b}, v19.16b 1.41 and v19.16b, v20.16b, v19.16b 1.14 umaxp v20.4s, v19.4s, v19.4s 1.50 mov x2, v20.d[0] 2.29 cmp x2, #0x0 ↓ b.ne 188 2.85 add x4, x4, #0x10 3.15 cmp x4, x0 ↑ b.cc 60 0.69 94: sub w0, w3, #0x8 mov w0, w0 0.90 add x0, x1, x0 0.79 cmp x4, x0 0.77 csel x4, x0, x4, hi // hi = pmore 0.69 ldr x2, [x4] 0.69 mov v17.d[0], x2 0.58 ldr x2, [x0] 0.90 mov v17.d[1], x2 0.62 movi v18.16b, #0xf 0.92 and v18.16b, v17.16b, v18.16b 0.79 tbl v16.16b, {v16.16b}, v18.16b 0.62 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1d0 1.37 sshr v17.16b, v17.16b, #4 0.54 tbl v17.16b, {v18.16b}, v17.16b and v16.16b, v16.16b, v17.16b 0.73 umaxp v17.4s, v16.4s, v16.4s 0.09 mov x2, v17.d[0] 0.58 cmp x2, #0x0 ↓ b.eq 180 4.03 cmeq v16.16b, v16.16b, #0 0.02 mvn v16.16b, v16.16b 0.36 shrn v16.8b, v16.8h, #4 0.15 mov x2, v16.d[0] 0.84 rbit x2, x2 0.06 clz x2, x2 0.84 lsr w2, w2, #2 0.71 mov w3, #0xffffffff // #-1 0.75 cmp w2, #0x10 csel w2, w2, w3, ne // ne = any 0.77 asr w3, w2, #0 0.73 cmp w3, #0x8 ↓ b.ge 1bc 44.58 118: sub x1, x4, x1 add w0, w1, w3 0.58 120: ldp x29, x30, [sp], #16 ← ret 128: mov x1, xzr mov w0, wzr ↑ b 18 134: mov w0, w0 add x0, x1, x0 cmp x1, x0 ↓ b.eq 180 144: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 178 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 144 ↓ b 180 178: sub x0, x4, x1 ↑ b 120 180: mov w0, #0xffffffff // #-1 ↑ b 120 188: cmeq v17.16b, v19.16b, #0 mvn v16.16b, v17.16b shrn v18.8b, v16.8h, #4 mov x3, v18.d[0] rbit x0, x3 clz x0, x0 lsr w0, w0, #2 mov w2, #0xffffffff // #-1 cmp w0, #0x10 csel w0, w0, w2, ne // ne = any sub x1, x4, x1 add w0, w1, w0 ↑ b 120 1bc: mov x4, x0 sub w3, w2, #0x8 ↑ b 118 Samples: 4K of event 'cpu-clock', 999 Hz, Event count (approx.): 5002001997, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-45752-25534.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 0.76 24: ldp x1, x22, [x19, #56] 2.29 ldr x0, [x1, #8] 0.76 ldr x1, [x1, #24] 0.38 → blr x1 1.53 stlur w0, [x22, #56] 1.15 ldr x0, [x19, #64] add x22, x0, #0x38 0.38 ldr x1, [x19, #56] 0.76 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.76 → blr x1 1.15 stlr w0, [x22] 0.76 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 0.76 ldr x0, [x1, #8] 1.53 ldr x1, [x1, #24] 0.38 → blr x1 1.15 stlr w0, [x22] 0.76 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 1.15 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.76 → blr x1 2.29 stlr w0, [x22] 0.38 ldr x0, [x19, #64] add x22, x0, #0x38 0.38 ldr x1, [x19, #56] 1.15 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.53 → blr x1 2.29 stlr w0, [x22] 0.38 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 1.53 ldr x0, [x1, #8] 0.76 ldr x1, [x1, #24] 1.15 → blr x1 0.38 stlr w0, [x22] 1.53 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 1.15 ldr x0, [x1, #8] 2.29 ldr x1, [x1, #24] 0.38 → blr x1 1.91 stlr w0, [x22] 0.76 ldr x0, [x19, #64] add x22, x0, #0x38 1.15 ldr x1, [x19, #56] 1.53 ldr x0, [x1, #8] 0.76 ldr x1, [x1, #24] 1.15 → blr x1 1.15 stlr w0, [x22] 1.53 ldr x0, [x19, #64] 3.82 add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 1.15 ldr x0, [x1, #8] 1.53 ldr x1, [x1, #24] 0.38 → blr x1 1.15 stlr w0, [x22] 0.76 ldr x0, [x19, #64] add x22, x0, #0x38 1.91 ldr x1, [x19, #56] 0.38 ldr x0, [x1, #8] 1.91 ldr x1, [x1, #24] 1.53 → blr x1 1.15 stlr w0, [x22] 0.38 ldr x0, [x19, #64] add x22, x0, #0x38 1.53 ldr x1, [x19, #56] 1.53 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.15 → blr x1 1.15 stlr w0, [x22] 1.91 ldr x0, [x19, #64] add x22, x0, #0x38 2.29 ldr x1, [x19, #56] 2.67 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.76 → blr x1 1.15 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] ldr x0, [x1, #8] 1.53 ldr x1, [x1, #24] → blr x1 3.05 stlr w0, [x22] 0.76 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 0.38 ldr x0, [x1, #8] 0.76 ldr x1, [x1, #24] 1.15 → blr x1 1.53 stlr w0, [x22] 0.38 ldr x0, [x19, #64] add x22, x0, #0x38 0.76 ldr x1, [x19, #56] 0.38 ldr x0, [x1, #8] 1.15 ldr x1, [x1, #24] 1.15 → blr x1 2.29 stlr w0, [x22] 0.38 ldr x0, [x19, #64] add x22, x0, #0x38 0.38 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.38 ldr x1, [x1, #24] 1.15 → blr x1 1.53 stlr w0, [x22] 0.76 add x21, x21, #0x1 0.76 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret