Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5074074069, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-45742-26752.so 0.62 stp x29, x30, [sp, #-16]! mov x29, sp 1.22 ldr x0, [x0, #8] 0.54 ↓ cbz x0, 130 0.45 add x1, x0, #0x10 0.62 ldr w0, [x0, #8] 18: mov x2, #0x2d18 // #11544 0.47 movk x2, #0xf900, lsl #16 0.51 movk x2, #0xe8e9, lsl #32 0.60 ldr x2, [x2] asr w3, w0, #0 0.69 add x2, x2, #0x8 0.47 mov x4, x1 0.71 cmp w3, #0x8 ↓ b.lt 13c 0.45 ldr q16, [x2] 0.79 cmp w3, #0x10 ↓ b.le 94 0.64 sub w0, w3, #0x10 mov w2, w0 0.49 add x0, x1, x2 movi v17.16b, #0xf 0.73 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 nop 3.08 60: ldr q19, [x4] 2.14 and v20.16b, v19.16b, v17.16b 0.02 tbl v20.16b, {v16.16b}, v20.16b 2.42 sshr v19.16b, v19.16b, #4 0.49 tbl v19.16b, {v18.16b}, v19.16b 1.80 and v19.16b, v20.16b, v19.16b 0.77 umaxp v20.4s, v19.4s, v19.4s 2.21 mov x2, v20.d[0] 2.23 cmp x2, #0x0 ↓ b.ne 190 2.89 add x4, x4, #0x10 2.12 cmp x4, x0 ↑ b.cc 60 0.54 94: sub w0, w3, #0x8 mov w0, w0 0.56 add x0, x1, x0 0.54 cmp x4, x0 0.39 csel x4, x0, x4, hi // hi = pmore 0.62 ldr x2, [x4] 0.66 mov v17.d[0], x2 0.64 ldr x2, [x0] 0.84 mov v17.d[1], x2 0.49 movi v18.16b, #0xf 0.66 and v18.16b, v17.16b, v18.16b 0.62 tbl v16.16b, {v16.16b}, v18.16b 0.43 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 0.99 sshr v17.16b, v17.16b, #4 0.69 tbl v17.16b, {v18.16b}, v17.16b 0.17 and v16.16b, v16.16b, v17.16b 0.71 umaxp v17.4s, v16.4s, v16.4s mov x2, v17.d[0] 0.56 cmp x2, #0x0 ↓ b.eq 188 2.42 cmeq v16.16b, v16.16b, #0 0.02 movi v17.16b, #0x80 0.58 and v16.16b, v16.16b, v17.16b 0.49 ldr q17, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 1.20 ushl v16.16b, v16.16b, v17.16b uxtl2 v17.8h, v16.16b 0.66 shl v17.8h, v17.8h, #8 0.60 uaddw v16.8h, v17.8h, v16.8b 0.51 addv h16, v16.8h 0.56 umov w2, v16.h[0] mvn w2, w2 0.58 rbit w2, w2 clz w2, w2 0.51 cmp w2, #0x8 ↓ b.ge 1d0 50.92 120: sub x1, x4, x1 add w0, w1, w2 0.66 128: ldp x29, x30, [sp], #16 ← ret 130: mov x1, xzr mov w0, wzr ↑ b 18 13c: mov w0, w0 add x0, x1, x0 cmp x1, x0 ↓ b.eq 188 14c: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 180 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 14c ↓ b 188 180: sub x0, x4, x1 ↑ b 128 188: mov w0, #0xffffffff // #-1 ↑ b 128 190: cmeq v17.16b, v19.16b, #0 movi v16.16b, #0x80 and v18.16b, v17.16b, v16.16b ldr q16, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 ushl v16.16b, v18.16b, v16.16b uxtl2 v17.8h, v16.16b shl v17.8h, v17.8h, #8 uaddw v16.8h, v17.8h, v16.8b addv h16, v16.8h umov w0, v16.h[0] mvn w0, w0 rbit w0, w0 clz w0, w0 sub x1, x4, x1 add w0, w0, w1 ↑ b 128 1d0: mov x4, x0 sub w2, w2, #0x8 ↑ b 120 Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5074074069, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-45742-25557.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 24: ldp x1, x22, [x19, #56] 0.84 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 1.26 → blr x1 1.67 stlur w0, [x22, #56] 0.84 ldr x0, [x19, #64] 1.26 add x22, x0, #0x38 1.26 ldr x1, [x19, #56] 1.26 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] → blr x1 1.26 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] 1.26 ldr x1, [x1, #24] 1.26 → blr x1 1.26 stlr w0, [x22] 1.26 ldr x0, [x19, #64] add x22, x0, #0x38 0.42 ldr x1, [x19, #56] 0.42 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 0.84 → blr x1 0.42 stlr w0, [x22] 0.42 ldr x0, [x19, #64] 0.84 add x22, x0, #0x38 1.26 ldr x1, [x19, #56] 0.42 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.67 → blr x1 1.67 stlr w0, [x22] 0.42 ldr x0, [x19, #64] 1.26 add x22, x0, #0x38 1.26 ldr x1, [x19, #56] 1.67 ldr x0, [x1, #8] 1.26 ldr x1, [x1, #24] 0.42 → blr x1 1.67 stlr w0, [x22] ldr x0, [x19, #64] 0.42 add x22, x0, #0x38 0.42 ldr x1, [x19, #56] 1.67 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 0.42 → blr x1 2.51 stlr w0, [x22] 1.67 ldr x0, [x19, #64] add x22, x0, #0x38 0.42 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 0.42 stlr w0, [x22] 0.84 ldr x0, [x19, #64] 1.67 add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.84 → blr x1 2.09 stlr w0, [x22] 0.84 ldr x0, [x19, #64] 0.84 add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 1.26 ldr x0, [x1, #8] 2.09 ldr x1, [x1, #24] → blr x1 2.09 stlr w0, [x22] 0.42 ldr x0, [x19, #64] 1.26 add x22, x0, #0x38 1.67 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] 0.42 ldr x1, [x1, #24] 0.42 → blr x1 1.26 stlr w0, [x22] 1.67 ldr x0, [x19, #64] 0.84 add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 0.42 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.67 → blr x1 0.84 stlr w0, [x22] 1.67 ldr x0, [x19, #64] 1.67 add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 1.67 ldr x0, [x1, #8] 1.26 ldr x1, [x1, #24] 0.42 → blr x1 1.26 stlr w0, [x22] ldr x0, [x19, #64] 0.84 add x22, x0, #0x38 0.42 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 1.67 stlr w0, [x22] 0.42 ldr x0, [x19, #64] 1.26 add x22, x0, #0x38 ldr x1, [x19, #56] 1.67 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] → blr x1 2.09 stlr w0, [x22] 0.84 ldr x0, [x19, #64] 0.42 add x22, x0, #0x38 0.84 ldr x1, [x19, #56] 0.84 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 0.84 → blr x1 2.09 stlr w0, [x22] 0.84 add x21, x21, #0x1 1.26 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret