Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5008008003, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-40471-26705.so 0.43 stp x29, x30, [sp, #-16]! 0.02 mov x29, sp 0.62 ldr x0, [x0, #8] 0.56 ↓ cbz x0, 130 0.31 add x1, x0, #0x10 0.29 ldr w0, [x0, #8] 0.02 18: mov x2, #0x2d18 // #11544 0.33 movk x2, #0xfdc0, lsl #16 0.29 movk x2, #0xe79f, lsl #32 0.41 ldr x2, [x2] 0.25 asr w3, w0, #0 0.06 add x2, x2, #0x8 0.19 mov x4, x1 0.45 cmp w3, #0x8 ↓ b.lt 13c 0.35 ldr q16, [x2] 0.33 cmp w3, #0x10 ↓ b.le 94 0.33 sub w0, w3, #0x10 mov w2, w0 0.58 add x0, x1, x2 movi v17.16b, #0xf 0.52 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 nop 1.47 60: ldr q19, [x4] 1.10 and v20.16b, v19.16b, v17.16b 0.17 tbl v20.16b, {v16.16b}, v20.16b 1.43 sshr v19.16b, v19.16b, #4 0.50 tbl v19.16b, {v18.16b}, v19.16b 1.08 and v19.16b, v20.16b, v19.16b 0.62 umaxp v20.4s, v19.4s, v19.4s 1.10 mov x2, v20.d[0] 1.51 cmp x2, #0x0 ↓ b.ne 190 3.49 add x4, x4, #0x10 1.80 cmp x4, x0 ↑ b.cc 60 0.39 94: sub w0, w3, #0x8 0.10 mov w0, w0 0.25 add x0, x1, x0 0.39 cmp x4, x0 0.23 csel x4, x0, x4, hi // hi = pmore 0.17 ldr x2, [x4] 0.45 mov v17.d[0], x2 0.39 ldr x2, [x0] 0.48 mov v17.d[1], x2 0.48 movi v18.16b, #0xf 0.02 and v18.16b, v17.16b, v18.16b 0.37 tbl v16.16b, {v16.16b}, v18.16b 0.31 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 0.48 sshr v17.16b, v17.16b, #4 0.21 tbl v17.16b, {v18.16b}, v17.16b 0.17 and v16.16b, v16.16b, v17.16b 0.21 umaxp v17.4s, v16.4s, v16.4s 0.25 mov x2, v17.d[0] 0.33 cmp x2, #0x0 ↓ b.eq 188 12.08 cmeq v16.16b, v16.16b, #0 movi v17.16b, #0x80 0.39 and v16.16b, v16.16b, v17.16b 0.27 ldr q17, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 0.37 ushl v16.16b, v16.16b, v17.16b 0.02 uxtl2 v17.8h, v16.16b 0.48 shl v17.8h, v17.8h, #8 0.37 uaddw v16.8h, v17.8h, v16.8b 0.37 addv h16, v16.8h 0.33 umov w2, v16.h[0] mvn w2, w2 0.39 rbit w2, w2 0.14 clz w2, w2 0.37 cmp w2, #0x8 ↓ b.ge 1d0 57.90 120: sub x1, x4, x1 add w0, w1, w2 0.25 128: ldp x29, x30, [sp], #16 ← ret 130: mov x1, xzr mov w0, wzr ↑ b 18 13c: mov w0, w0 add x0, x1, x0 cmp x4, x0 ↓ b.eq 188 14c: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 180 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 14c ↓ b 188 180: sub x0, x4, x1 ↑ b 128 188: mov w0, #0xffffffff // #-1 ↑ b 128 190: cmeq v17.16b, v19.16b, #0 movi v16.16b, #0x80 and v18.16b, v17.16b, v16.16b ldr q16, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 ushl v16.16b, v18.16b, v16.16b uxtl2 v17.8h, v16.16b shl v17.8h, v17.8h, #8 uaddw v16.8h, v17.8h, v16.8b addv h16, v16.8h umov w0, v16.h[0] mvn w0, w0 rbit w0, w0 clz w0, w0 sub x1, x4, x1 add w0, w0, w1 ↑ b 128 1d0: mov x4, x0 sub w2, w2, #0x8 ↑ b 120 Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5008008003, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-40471-25510.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 0.80 24: ldp x1, x22, [x19, #56] ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] → blr x1 0.80 stlur w0, [x22, #56] 1.60 ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 4.00 → blr x1 0.80 stlr w0, [x22] 1.60 ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 2.40 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 0.80 → blr x1 1.60 stlr w0, [x22] 3.20 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 4.80 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 1.60 ldr x1, [x19, #56] 1.60 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 1.60 → blr x1 0.80 stlr w0, [x22] 1.60 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] → blr x1 1.60 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] ldr x0, [x1, #8] 1.60 ldr x1, [x1, #24] 0.80 → blr x1 1.60 stlr w0, [x22] 1.60 ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 1.60 ldr x0, [x1, #8] 1.60 ldr x1, [x1, #24] → blr x1 2.40 stlr w0, [x22] 1.60 ldr x0, [x19, #64] 0.80 add x22, x0, #0x38 1.60 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.80 → blr x1 2.40 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 1.60 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] → blr x1 0.80 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] ldr x0, [x1, #8] 1.60 ldr x1, [x1, #24] → blr x1 1.60 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 0.80 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 1.60 ldr x1, [x19, #56] 3.20 ldr x0, [x1, #8] 1.60 ldr x1, [x1, #24] 0.80 → blr x1 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] → blr x1 2.40 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 0.80 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 1.60 → blr x1 4.00 stlr w0, [x22] 0.80 ldr x0, [x19, #64] add x22, x0, #0x38 1.60 ldr x1, [x19, #56] 0.80 ldr x0, [x1, #8] 1.60 ldr x1, [x1, #24] 3.20 → blr x1 stlr w0, [x22] 1.60 add x21, x21, #0x1 0.80 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret