Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5002200240, [percent: local period] instance int32 [benchapp] MinMaxBench::Max()[OptimizedTier1]() /tmp/jitted-46049-26917.so 1.38 stp x29, x30, [sp, #-48]! 2.73 stp x19, x20, [sp, #24] 1.36 str x21, [sp, #40] 1.32 mov x29, sp 1.37 ldr x19, [x0, #8] 2.44 ↓ cbz x19, b4 2.23 mov w20, #0x1 // #1 1.41 ldr x0, [x19] 6.92 mov x1, #0xba78 // #47736 0.53 movk x1, #0xc52b, lsl #16 0.71 movk x1, #0xedcd, lsl #32 1.51 cmp x0, x1 ↓ b.ne d0 3.34 add x2, x19, #0x10 1.38 ldr w3, [x19, #8] 1.78 3c: ↓ cbz w20, 190 1.44 ↓ cbz w3, 148 3.11 cmp w3, #0x4 ↓ b.lt 160 1.46 sub w3, w3, #0x4 0.13 ubfiz x0, x3, #2, #32 1.24 add x0, x2, x0 1.32 ldr q16, [x2], #16 5.30 cmp x2, x0 ↓ b.cs 74 13.59 64: ldr q17, [x2], #16 6.24 smax v16.4s, v16.4s, v17.4s 2.83 cmp x2, x0 ↑ b.cc 64 2.45 74: ldr q17, [x0] 16.37 smax v16.4s, v16.4s, v17.4s 0.56 smov x0, v16.s[0] 1.47 smov x1, v16.s[1] 1.44 cmp w1, w0 csel w0, w0, w1, le 1.37 smov x1, v16.s[2] 1.41 cmp w1, w0 csel w0, w0, w1, le 1.21 smov x1, v16.s[3] 1.36 cmp w1, w0 csel w0, w0, w1, le 2.56 a4: ldr x21, [sp, #40] 1.34 ldp x19, x20, [sp, #24] 1.40 ldp x29, x30, [sp], #48 ← ret b4: mov w0, #0x11 // #17 mov x1, #0x61f0 // #25072 movk x1, #0xc547, lsl #16 movk x1, #0xedcd, lsl #32 ldr x1, [x1] → blr x1 brk #0xf000 d0: ldr x0, [x19] mov x1, #0x73b0 // #29616 movk x1, #0xc560, lsl #16 movk x1, #0xedcd, lsl #32 cmp x0, x1 ↓ b.ne 138 ldr w1, [x19, #16] ldr x0, [x19, #8] ldr w2, [x0, #8] cmp w2, w1 ↓ b.cs 114 mov x0, #0x7030 // #28720 movk x0, #0xc547, lsl #16 movk x0, #0xedcd, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 114: add x0, x0, #0x10 mov x2, #0x6a60 // #27232 movk x2, #0xc57d, lsl #16 movk x2, #0xedcd, lsl #32 ldr x2, [x2] → blr x2 mov x2, x0 mov w3, w1 ↑ b 3c 138: mov x2, xzr mov w3, wzr mov w20, wzr ↑ b 3c 148: mov x0, #0x7d50 // #32080 movk x0, #0xc55f, lsl #16 movk x0, #0xedcd, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 160: ldr w0, [x2] mov w1, #0x1 // #1 cmp w1, w3 ↑ b.ge a4 170: ldr w4, [x2, w1, uxtw #2] cmp w4, w0 ↓ b.le 180 ldr w0, [x2, w1, uxtw #2] 180: add w1, w1, #0x1 cmp w1, w3 ↑ b.lt 170 ↑ b a4 190: ldr w20, [x19, #8] ↓ cbz w20, 1d4 mov x0, #0xec68 // #60520 movk x0, #0xc5e2, lsl #16 movk x0, #0xedcd, lsl #32 bl ffffffffff6f9ab0 mov x21, x0 mov w1, w20 mov x2, #0x4618 // #17944 movk x2, #0xc57d, lsl #16 movk x2, #0xedcd, lsl #32 ldr x2, [x2] → blr x2 add x14, x21, #0x10 mov x15, x19 bl fffffffffe467d74 ↓ b 204 1d4: mov x0, #0xec68 // #60520 movk x0, #0xc5e2, lsl #16 movk x0, #0xedcd, lsl #32 mov x1, #0x5728 // #22312 movk x1, #0xc528, lsl #16 movk x1, #0xedcd, lsl #32 ldr x1, [x1] → blr x1 mov x0, #0x2e00 // #11776 movk x0, #0x500, lsl #16 movk x0, #0xedc6, lsl #32 ldr x21, [x0] 204: ldp w0, w1, [x21, #8] add w0, w0, #0x1 cmp w0, w1 ↓ b.cs 234 str w0, [x21, #8] mov x0, x21 mov x1, #0xed28 // #60712 movk x1, #0xc5e2, lsl #16 movk x1, #0xedcd, lsl #32 ldr x1, [x1] → blr x1 ↓ b 288 234: ldr w0, [x21, #12] str w0, [x21, #8] mov x0, #0x7d50 // #32080 movk x0, #0xc55f, lsl #16 movk x0, #0xedcd, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 254: ldp w1, w2, [x21, #8] cmp w1, w2 ↓ b.cs 2b8 ldr x1, [x21, #16] ldr w2, [x21, #8] ldr w3, [x1, #8] cmp w2, w3 ↓ b.cs 2d4 add x1, x1, #0x10 ldr w1, [x1, w2, uxtw #2] cmp w1, w0 ↓ b.le 288 asr w0, w1, #0 288: ldr w1, [x21, #8] add w1, w1, #0x1 ldr w2, [x21, #12] cmp w1, w2 ↓ b.cs 2a4 str w1, [x21, #8] ↑ b 254 2a4: ldr w1, [x21, #12] str w1, [x21, #8] mov w1, wzr ↑ cbnz w1, 254 ↑ b a4 2b8: ldr w0, [x21, #8] mov x1, #0xd4e8 // #54504 movk x1, #0xc57d, lsl #16 movk x1, #0xedcd, lsl #32 ldr x1, [x1] → blr x1 brk #0xf000 2d4: bl ffffffffff6a94c8 brk #0xf000 Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5002200240, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-46049-25759.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 0.84 24: ldp x1, x22, [x19, #64] 0.84 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 0.88 → blr x1 1.46 stlur w0, [x22, #56] 0.84 ldr x0, [x19, #72] 0.04 add x22, x0, #0x38 0.93 ldr x1, [x19, #64] 1.19 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 0.75 → blr x1 1.77 stlr w0, [x22] 0.62 ldr x0, [x19, #72] add x22, x0, #0x38 0.80 ldr x1, [x19, #64] 0.75 ldr x0, [x1, #8] 0.66 ldr x1, [x1, #24] 0.88 → blr x1 1.77 stlr w0, [x22] 0.88 ldr x0, [x19, #72] 0.09 add x22, x0, #0x38 0.97 ldr x1, [x19, #64] 0.75 ldr x0, [x1, #8] 1.06 ldr x1, [x1, #24] 1.11 → blr x1 1.46 stlr w0, [x22] 0.75 ldr x0, [x19, #72] add x22, x0, #0x38 0.66 ldr x1, [x19, #64] 0.84 ldr x0, [x1, #8] 0.93 ldr x1, [x1, #24] 1.02 → blr x1 1.73 stlr w0, [x22] 0.66 ldr x0, [x19, #72] 0.04 add x22, x0, #0x38 0.84 ldr x1, [x19, #64] 1.15 ldr x0, [x1, #8] 0.75 ldr x1, [x1, #24] 1.15 → blr x1 1.50 stlr w0, [x22] 0.97 ldr x0, [x19, #72] add x22, x0, #0x38 1.11 ldr x1, [x19, #64] 0.62 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 0.84 → blr x1 1.55 stlr w0, [x22] 0.62 ldr x0, [x19, #72] add x22, x0, #0x38 0.88 ldr x1, [x19, #64] 0.80 ldr x0, [x1, #8] 0.80 ldr x1, [x1, #24] 0.88 → blr x1 1.64 stlr w0, [x22] 0.93 ldr x0, [x19, #72] 1.28 add x22, x0, #0x38 1.02 ldr x1, [x19, #64] 0.80 ldr x0, [x1, #8] 1.06 ldr x1, [x1, #24] 1.11 → blr x1 2.04 stlr w0, [x22] 0.84 ldr x0, [x19, #72] add x22, x0, #0x38 1.15 ldr x1, [x19, #64] 0.58 ldr x0, [x1, #8] 1.06 ldr x1, [x1, #24] 1.42 → blr x1 1.37 stlr w0, [x22] 0.62 ldr x0, [x19, #72] add x22, x0, #0x38 1.02 ldr x1, [x19, #64] 0.88 ldr x0, [x1, #8] 0.75 ldr x1, [x1, #24] 1.06 → blr x1 1.59 stlr w0, [x22] 1.28 ldr x0, [x19, #72] 0.04 add x22, x0, #0x38 1.46 ldr x1, [x19, #64] 0.88 ldr x0, [x1, #8] 0.84 ldr x1, [x1, #24] 1.06 → blr x1 2.35 stlr w0, [x22] 0.88 ldr x0, [x19, #72] add x22, x0, #0x38 0.75 ldr x1, [x19, #64] 0.75 ldr x0, [x1, #8] 0.97 ldr x1, [x1, #24] 0.84 → blr x1 1.68 stlr w0, [x22] 1.19 ldr x0, [x19, #72] 0.04 add x22, x0, #0x38 0.71 ldr x1, [x19, #64] 0.62 ldr x0, [x1, #8] 0.88 ldr x1, [x1, #24] 0.66 → blr x1 1.68 stlr w0, [x22] 0.40 ldr x0, [x19, #72] add x22, x0, #0x38 0.80 ldr x1, [x19, #64] 0.97 ldr x0, [x1, #8] 0.97 ldr x1, [x1, #24] 0.84 → blr x1 1.81 stlr w0, [x22] 1.24 ldr x0, [x19, #72] add x22, x0, #0x38 0.62 ldr x1, [x19, #64] 0.58 ldr x0, [x1, #8] 0.97 ldr x1, [x1, #24] 0.80 → blr x1 1.50 stlr w0, [x22] 0.66 add x21, x21, #0x1 0.66 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5002200240, [percent: local period] stub<18947> Allocate() /tmp/jitted-46049-24820.so 33.69 ldr x11, stub<18947 66.31 → br x11 dmb ishld ldr x12, stub<18947 ldr x11, stub<18947 → br x11