Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5069013600, [percent: local period] instance int32 [benchapp] MinMaxBench::Max()[OptimizedTier1]() /tmp/jitted-45985-26999.so 1.19 stp x29, x30, [sp, #-48]! 2.29 stp x19, x20, [sp, #24] 1.12 str x21, [sp, #40] 1.01 mov x29, sp 1.04 ldr x19, [x0, #8] 2.70 ↓ cbz x19, e0 1.83 mov w20, #0x1 // #1 1.07 ldr x0, [x19] 6.37 mov x1, #0xba78 // #47736 0.05 movk x1, #0xbd2a, lsl #16 1.05 movk x1, #0xe327, lsl #32 1.08 cmp x0, x1 ↓ b.ne fc 2.83 add x2, x19, #0x10 1.15 ldr w3, [x19, #8] 1.24 3c: ↓ cbz w20, 1f0 1.11 ↓ cbz w3, 174 2.63 cmp w3, #0x4 ↓ b.lt 18c 1.26 sub w0, w3, #0x4 0.00 asr w1, w0, #0 1.07 cmp w1, w3 ↓ b.hi 1bc 5.67 ubfiz x4, x1, #2, #32 1.17 add x4, x2, x4 sub w1, w3, w1 1.02 ldr q16, [x2], #16 1.20 asr w3, w0, #0 1.17 cmp w3, #0x4 ↓ b.lt 98 2.62 nop nop 9.18 80: ldr q17, [x2] 8.84 smax v16.4s, v16.4s, v17.4s 0.99 add x2, x2, #0x10 2.37 sub w3, w3, #0x4 3.24 cmp w3, #0x4 ↑ b.ge 80 3.52 98: cmp w1, #0x4 ↓ b.lt 1d4 1.20 ldr q17, [x4] 15.94 smax v16.4s, v16.4s, v17.4s smov x0, v16.s[0] 1.06 smov x1, v16.s[1] 1.02 cmp w1, w0 csel w0, w0, w1, le 1.15 smov x1, v16.s[2] 1.08 cmp w1, w0 csel w0, w0, w1, le 0.05 smov x1, v16.s[3] 2.12 cmp w1, w0 csel w0, w0, w1, le 1.10 d0: ldr x21, [sp, #40] 1.08 ldp x19, x20, [sp, #24] 1.11 ldp x29, x30, [sp], #48 ← ret e0: mov w0, #0x11 // #17 mov x1, #0x61f0 // #25072 movk x1, #0xbd46, lsl #16 movk x1, #0xe327, lsl #32 ldr x1, [x1] → blr x1 brk #0xf000 fc: ldr x0, [x19] mov x1, #0x73b0 // #29616 movk x1, #0xbd5f, lsl #16 movk x1, #0xe327, lsl #32 cmp x0, x1 ↓ b.ne 164 ldr w1, [x19, #16] ldr x0, [x19, #8] ldr w2, [x0, #8] cmp w2, w1 ↓ b.cs 140 mov x0, #0x7030 // #28720 movk x0, #0xbd46, lsl #16 movk x0, #0xe327, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 140: add x0, x0, #0x10 mov x2, #0x6a60 // #27232 movk x2, #0xbd7c, lsl #16 movk x2, #0xe327, lsl #32 ldr x2, [x2] → blr x2 mov x2, x0 mov w3, w1 ↑ b 3c 164: mov x2, xzr mov w3, wzr mov w20, wzr ↑ b 3c 174: mov x0, #0x7d50 // #32080 movk x0, #0xbd5e, lsl #16 movk x0, #0xe327, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 18c: ldr w0, [x2] mov w1, #0x1 // #1 cmp w1, w3 ↑ b.ge d0 19c: ldr w4, [x2, w1, uxtw #2] cmp w4, w0 ↓ b.le 1ac ldr w0, [x2, w1, uxtw #2] 1ac: add w1, w1, #0x1 cmp w1, w3 ↑ b.lt 19c ↑ b d0 1bc: mov x0, #0xdb18 // #56088 movk x0, #0xbd46, lsl #16 movk x0, #0xe327, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 1d4: mov w0, #0x6 // #6 mov x1, #0x6ec8 // #28360 movk x1, #0xbd46, lsl #16 movk x1, #0xe327, lsl #32 ldr x1, [x1] → blr x1 brk #0xf000 1f0: ldr w20, [x19, #8] ↓ cbz w20, 234 mov x0, #0x3360 // #13152 movk x0, #0xbdec, lsl #16 movk x0, #0xe327, lsl #32 bl ffffffffff6f9830 mov x21, x0 mov w1, w20 mov x2, #0x4618 // #17944 movk x2, #0xbd7c, lsl #16 movk x2, #0xe327, lsl #32 ldr x2, [x2] → blr x2 add x14, x21, #0x10 mov x15, x19 bl fffffffffe467af4 ↓ b 264 234: mov x0, #0x3360 // #13152 movk x0, #0xbdec, lsl #16 movk x0, #0xe327, lsl #32 mov x1, #0x5728 // #22312 movk x1, #0xbd27, lsl #16 movk x1, #0xe327, lsl #32 ldr x1, [x1] → blr x1 mov x0, #0x2e00 // #11776 movk x0, #0xfd00, lsl #16 movk x0, #0xe31f, lsl #32 ldr x21, [x0] 264: ldp w0, w1, [x21, #8] add w0, w0, #0x1 cmp w0, w1 ↓ b.cs 294 str w0, [x21, #8] mov x0, x21 mov x1, #0x3420 // #13344 movk x1, #0xbdec, lsl #16 movk x1, #0xe327, lsl #32 ldr x1, [x1] → blr x1 ↓ b 2e8 294: ldr w0, [x21, #12] str w0, [x21, #8] mov x0, #0x7d50 // #32080 movk x0, #0xbd5e, lsl #16 movk x0, #0xe327, lsl #32 ldr x0, [x0] → blr x0 brk #0xf000 2b4: ldp w1, w2, [x21, #8] cmp w1, w2 ↓ b.cs 318 ldr x1, [x21, #16] ldr w2, [x21, #8] ldr w3, [x1, #8] cmp w2, w3 ↓ b.cs 334 add x1, x1, #0x10 ldr w1, [x1, w2, uxtw #2] cmp w1, w0 ↓ b.le 2e8 asr w0, w1, #0 2e8: ldr w1, [x21, #8] add w1, w1, #0x1 ldr w2, [x21, #12] cmp w1, w2 ↓ b.cs 304 str w1, [x21, #8] ↑ b 2b4 304: ldr w1, [x21, #12] str w1, [x21, #8] mov w1, wzr ↑ cbnz w1, 2b4 ↑ b d0 318: ldr w0, [x21, #8] mov x1, #0xd4e8 // #54504 movk x1, #0xbd7c, lsl #16 movk x1, #0xe327, lsl #32 ldr x1, [x1] → blr x1 brk #0xf000 334: bl ffffffffff6a9248 brk #0xf000 Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5069013600, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-45985-25820.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 0.86 24: ldp x1, x22, [x19, #64] 0.54 ldr x0, [x1, #8] 0.81 ldr x1, [x1, #24] 1.30 → blr x1 1.62 stlur w0, [x22, #56] 0.86 ldr x0, [x19, #72] add x22, x0, #0x38 0.92 ldr x1, [x19, #64] 0.76 ldr x0, [x1, #8] 1.13 ldr x1, [x1, #24] 1.13 → blr x1 1.40 stlr w0, [x22] 0.54 ldr x0, [x19, #72] add x22, x0, #0x38 0.70 ldr x1, [x19, #64] 0.49 ldr x0, [x1, #8] 0.81 ldr x1, [x1, #24] 1.24 → blr x1 1.35 stlr w0, [x22] 0.81 ldr x0, [x19, #72] add x22, x0, #0x38 1.08 ldr x1, [x19, #64] 0.49 ldr x0, [x1, #8] 0.97 ldr x1, [x1, #24] 1.40 → blr x1 1.30 stlr w0, [x22] 0.70 ldr x0, [x19, #72] add x22, x0, #0x38 0.81 ldr x1, [x19, #64] 1.03 ldr x0, [x1, #8] 1.51 ldr x1, [x1, #24] 1.40 → blr x1 1.67 stlr w0, [x22] 0.70 ldr x0, [x19, #72] add x22, x0, #0x38 0.76 ldr x1, [x19, #64] 0.49 ldr x0, [x1, #8] 0.86 ldr x1, [x1, #24] 0.86 → blr x1 1.46 stlr w0, [x22] 0.49 ldr x0, [x19, #72] add x22, x0, #0x38 0.81 ldr x1, [x19, #64] 0.59 ldr x0, [x1, #8] 1.30 ldr x1, [x1, #24] 0.76 → blr x1 1.57 stlr w0, [x22] 0.54 ldr x0, [x19, #72] add x22, x0, #0x38 0.59 ldr x1, [x19, #64] 1.24 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 0.65 → blr x1 2.05 stlr w0, [x22] 1.03 ldr x0, [x19, #72] 0.92 add x22, x0, #0x38 0.81 ldr x1, [x19, #64] 0.86 ldr x0, [x1, #8] 1.08 ldr x1, [x1, #24] 0.86 → blr x1 1.73 stlr w0, [x22] 0.97 ldr x0, [x19, #72] add x22, x0, #0x38 0.70 ldr x1, [x19, #64] 0.81 ldr x0, [x1, #8] 1.08 ldr x1, [x1, #24] 0.70 → blr x1 2.00 stlr w0, [x22] 0.59 ldr x0, [x19, #72] add x22, x0, #0x38 0.97 ldr x1, [x19, #64] 0.97 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 0.97 → blr x1 1.73 stlr w0, [x22] 1.30 ldr x0, [x19, #72] add x22, x0, #0x38 0.59 ldr x1, [x19, #64] 0.70 ldr x0, [x1, #8] 0.81 ldr x1, [x1, #24] 1.30 → blr x1 1.62 stlr w0, [x22] 0.81 ldr x0, [x19, #72] add x22, x0, #0x38 0.97 ldr x1, [x19, #64] 0.97 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 0.81 → blr x1 1.89 stlr w0, [x22] 0.70 ldr x0, [x19, #72] add x22, x0, #0x38 0.81 ldr x1, [x19, #64] 1.19 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 1.46 → blr x1 1.57 stlr w0, [x22] 0.86 ldr x0, [x19, #72] add x22, x0, #0x38 0.86 ldr x1, [x19, #64] 0.76 ldr x0, [x1, #8] 1.24 ldr x1, [x1, #24] 0.59 → blr x1 0.86 stlr w0, [x22] 0.86 ldr x0, [x19, #72] add x22, x0, #0x38 1.19 ldr x1, [x19, #64] 1.19 ldr x0, [x1, #8] 0.97 ldr x1, [x1, #24] 0.81 → blr x1 1.73 stlr w0, [x22] 0.54 add x21, x21, #0x1 0.86 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret Samples: 25K of event 'cpu-clock', 4999 Hz, Event count (approx.): 5069013600, [percent: local period] stub<18991> Allocate() /tmp/jitted-45985-24884.so 40.05 ldr x11, stub<18991 59.95 → br x11 dmb ishld ldr x12, stub<18991 ldr x11, stub<18991 → br x11