Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5006006001, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-40541-26712.so 0.44 stp x29, x30, [sp, #-16]! 0.02 mov x29, sp 0.62 ldr x0, [x0, #8] 0.29 ↓ cbz x0, 130 0.29 add x1, x0, #0x10 0.29 ldr w0, [x0, #8] 0.06 18: mov x2, #0x2d18 // #11544 0.42 movk x2, #0x45c0, lsl #16 0.42 movk x2, #0xfbae, lsl #32 0.40 ldr x2, [x2] 0.12 asr w3, w0, #0 0.15 add x2, x2, #0x8 0.15 mov x4, x1 0.46 cmp w3, #0x8 ↓ b.lt 13c 0.29 ldr q16, [x2] 0.31 cmp w3, #0x10 ↓ b.le 94 0.44 sub w0, w3, #0x10 mov w2, w0 0.35 add x0, x1, x2 movi v17.16b, #0xf 0.25 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 0.02 nop 1.69 60: ldr q19, [x4] 1.27 and v20.16b, v19.16b, v17.16b 0.23 tbl v20.16b, {v16.16b}, v20.16b 1.21 sshr v19.16b, v19.16b, #4 0.54 tbl v19.16b, {v18.16b}, v19.16b 1.23 and v19.16b, v20.16b, v19.16b 0.50 umaxp v20.4s, v19.4s, v19.4s 1.29 mov x2, v20.d[0] 1.29 cmp x2, #0x0 ↓ b.ne 190 3.37 add x4, x4, #0x10 1.52 cmp x4, x0 ↑ b.cc 60 0.48 94: sub w0, w3, #0x8 0.17 mov w0, w0 0.17 add x0, x1, x0 0.48 cmp x4, x0 0.25 csel x4, x0, x4, hi // hi = pmore 0.35 ldr x2, [x4] 0.44 mov v17.d[0], x2 0.31 ldr x2, [x0] 0.40 mov v17.d[1], x2 0.33 movi v18.16b, #0xf and v18.16b, v17.16b, v18.16b 0.42 tbl v16.16b, {v16.16b}, v18.16b 0.29 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1e0 0.40 sshr v17.16b, v17.16b, #4 0.19 tbl v17.16b, {v18.16b}, v17.16b 0.25 and v16.16b, v16.16b, v17.16b 0.19 umaxp v17.4s, v16.4s, v16.4s 0.25 mov x2, v17.d[0] 0.42 cmp x2, #0x0 ↓ b.eq 188 12.21 cmeq v16.16b, v16.16b, #0 0.02 movi v17.16b, #0x80 0.35 and v16.16b, v16.16b, v17.16b 0.29 ldr q17, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 0.46 ushl v16.16b, v16.16b, v17.16b 0.02 uxtl2 v17.8h, v16.16b 0.31 shl v17.8h, v17.8h, #8 0.35 uaddw v16.8h, v17.8h, v16.8b 0.37 addv h16, v16.8h 0.50 umov w2, v16.h[0] mvn w2, w2 0.44 rbit w2, w2 0.17 clz w2, w2 0.31 cmp w2, #0x8 ↓ b.ge 1d0 58.04 120: sub x1, x4, x1 add w0, w1, w2 0.48 128: ldp x29, x30, [sp], #16 ← ret 130: mov x1, xzr mov w0, wzr ↑ b 18 13c: mov w0, w0 add x0, x1, x0 cmp x1, x0 ↓ b.eq 188 14c: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 180 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 14c ↓ b 188 180: sub x0, x4, x1 ↑ b 128 188: mov w0, #0xffffffff // #-1 ↑ b 128 190: cmeq v17.16b, v19.16b, #0 movi v16.16b, #0x80 and v18.16b, v17.16b, v16.16b ldr q16, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1f0 ushl v16.16b, v18.16b, v16.16b uxtl2 v17.8h, v16.16b shl v17.8h, v17.8h, #8 uaddw v16.8h, v17.8h, v16.8b addv h16, v16.8h umov w0, v16.h[0] mvn w0, w0 rbit w0, w0 clz w0, w0 sub x1, x4, x1 add w0, w0, w1 ↑ b 128 1d0: mov x4, x0 sub w2, w2, #0x8 ↑ b 120 Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5006006001, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-40541-25517.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 0.73 24: ldp x1, x22, [x19, #56] 1.46 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 0.73 stlur w0, [x22, #56] 0.73 ldr x0, [x19, #64] add x22, x0, #0x38 0.73 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 0.73 → blr x1 1.46 stlr w0, [x22] 0.73 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 1.46 ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] → blr x1 2.92 stlr w0, [x22] 2.92 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] 2.19 ldr x1, [x1, #24] 1.46 → blr x1 0.73 stlr w0, [x22] 1.46 ldr x0, [x19, #64] add x22, x0, #0x38 1.46 ldr x1, [x19, #56] ldr x0, [x1, #8] ldr x1, [x1, #24] 0.73 → blr x1 2.92 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 1.46 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 1.46 → blr x1 2.92 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 1.46 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 2.19 ldr x0, [x1, #8] 2.19 ldr x1, [x1, #24] 0.73 → blr x1 2.92 stlr w0, [x22] ldr x0, [x19, #64] 0.73 add x22, x0, #0x38 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 0.73 → blr x1 2.19 stlr w0, [x22] 0.73 ldr x0, [x19, #64] add x22, x0, #0x38 0.73 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 0.73 → blr x1 2.19 stlr w0, [x22] 0.73 ldr x0, [x19, #64] add x22, x0, #0x38 1.46 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 0.73 → blr x1 4.38 stlr w0, [x22] 2.19 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] 1.46 ldr x1, [x1, #24] 1.46 → blr x1 2.92 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 1.46 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.46 → blr x1 0.73 stlr w0, [x22] 0.73 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 2.19 ldr x0, [x1, #8] ldr x1, [x1, #24] 4.38 → blr x1 2.92 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.46 → blr x1 1.46 stlr w0, [x22] 1.46 ldr x0, [x19, #64] add x22, x0, #0x38 0.73 ldr x1, [x19, #56] 0.73 ldr x0, [x1, #8] 0.73 ldr x1, [x1, #24] 2.92 → blr x1 stlr w0, [x22] 2.19 add x21, x21, #0x1 2.19 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret