Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5086086081, [percent: local period] instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]() /tmp/jitted-40417-26724.so 0.52 stp x29, x30, [sp, #-16]! 0.35 mov x29, sp 0.81 ldr x0, [x0, #8] 0.37 ↓ cbz x0, 128 0.56 add x1, x0, #0x10 0.37 ldr w0, [x0, #8] 0.10 18: mov x2, #0x2d18 // #11544 0.31 movk x2, #0xdc0, lsl #16 0.46 movk x2, #0xe11a, lsl #32 0.46 ldr x2, [x2] 0.19 asr w3, w0, #0 0.31 add x2, x2, #0x8 0.12 mov x4, x1 0.42 cmp w3, #0x8 ↓ b.lt 134 0.48 ldr q16, [x2] 0.54 cmp w3, #0x10 ↓ b.le 94 0.37 sub w0, w3, #0x10 mov w2, w0 0.50 add x0, x1, x2 movi v17.16b, #0xf 0.42 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1d0 0.25 nop 1.81 60: ldr q19, [x4] 1.85 and v20.16b, v19.16b, v17.16b 0.08 tbl v20.16b, {v16.16b}, v20.16b 1.92 sshr v19.16b, v19.16b, #4 0.60 tbl v19.16b, {v18.16b}, v19.16b 1.23 and v19.16b, v20.16b, v19.16b 0.83 umaxp v20.4s, v19.4s, v19.4s 1.31 mov x2, v20.d[0] 1.92 cmp x2, #0x0 ↓ b.ne 188 12.84 add x4, x4, #0x10 1.52 cmp x4, x0 ↑ b.cc 60 0.42 94: sub w0, w3, #0x8 0.08 mov w0, w0 0.33 add x0, x1, x0 0.65 cmp x4, x0 0.10 csel x4, x0, x4, hi // hi = pmore 0.54 ldr x2, [x4] 0.62 mov v17.d[0], x2 0.42 ldr x2, [x0] 0.56 mov v17.d[1], x2 0.48 movi v18.16b, #0xf and v18.16b, v17.16b, v18.16b 0.56 tbl v16.16b, {v16.16b}, v18.16b 0.56 ldr q18, instance int32 [benchapp] Benchmarks::Medium()[OptimizedTier1]+0x1d0 0.42 sshr v17.16b, v17.16b, #4 0.21 tbl v17.16b, {v18.16b}, v17.16b 0.31 and v16.16b, v16.16b, v17.16b 0.25 umaxp v17.4s, v16.4s, v16.4s 0.02 mov x2, v17.d[0] 0.29 cmp x2, #0x0 ↓ b.eq 180 19.15 cmeq v16.16b, v16.16b, #0 0.15 mvn v16.16b, v16.16b 0.33 shrn v16.8b, v16.8h, #4 0.12 mov x2, v16.d[0] 0.17 rbit x2, x2 0.15 clz x2, x2 0.40 lsr w2, w2, #2 0.40 mov w3, #0xffffffff // #-1 0.42 cmp w2, #0x10 csel w2, w2, w3, ne // ne = any 0.35 asr w3, w2, #0 0.58 cmp w3, #0x8 ↓ b.ge 1bc 36.68 118: sub x1, x4, x1 0.04 add w0, w1, w3 0.40 120: ldp x29, x30, [sp], #16 ← ret 128: mov x1, xzr mov w0, wzr ↑ b 18 134: mov w0, w0 add x0, x1, x0 cmp x4, x0 ↓ b.eq 180 144: ldrb w3, [x4] add x5, x2, #0x20 asr w6, w3, #5 mov w7, #0x1 // #1 lsl w3, w7, w3 ldrsb wzr, [x5] ldr w5, [x5, w6, uxtw #2] tst w5, w3 ↓ b.ne 178 add x4, x4, #0x1 cmp x4, x0 ↑ b.ne 144 ↓ b 180 178: sub x0, x4, x1 ↑ b 120 180: mov w0, #0xffffffff // #-1 ↑ b 120 188: cmeq v17.16b, v19.16b, #0 mvn v16.16b, v17.16b shrn v18.8b, v16.8h, #4 mov x3, v18.d[0] rbit x0, x3 clz x0, x0 lsr w0, w0, #2 mov w2, #0xffffffff // #-1 cmp w0, #0x10 csel w0, w0, w2, ne // ne = any sub x1, x4, x1 add w0, w1, w0 ↑ b 120 1bc: mov x4, x0 sub w3, w2, #0x8 ↑ b 118 Samples: 5K of event 'cpu-clock', 999 Hz, Event count (approx.): 5086086081, [percent: local period] instance void [benchapp-Job-RTQYDZ-1Emitted] BenchmarkDotNet.Autogenerated.Runnable_0::WorkloadActionUnroll(int64)[Optimized]() /tmp/jitted-40417-25514.so Percent stp x29, x30, [sp, #-48]! stp x19, x20, [sp, #16] stp x21, x22, [sp, #32] mov x29, sp mov x19, x0 mov x20, x1 mov x21, xzr cmp x21, x20 ↓ b.ge 1e8 1.40 24: ldp x1, x22, [x19, #56] 1.40 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.70 → blr x1 1.40 stlur w0, [x22, #56] 1.40 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] 1.40 → blr x1 stlr w0, [x22] 2.10 ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 2.80 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 3.50 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.70 → blr x1 0.70 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 1.40 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] 0.70 → blr x1 2.80 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 1.40 ldr x1, [x19, #56] 0.70 ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] 1.40 → blr x1 2.10 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 ldr x1, [x19, #56] 0.70 ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] → blr x1 2.80 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] 0.70 ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] → blr x1 1.40 stlr w0, [x22] 0.70 ldr x0, [x19, #64] 2.10 add x22, x0, #0x38 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] 1.40 ldr x1, [x1, #24] → blr x1 3.50 stlr w0, [x22] ldr x0, [x19, #64] add x22, x0, #0x38 2.10 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] 1.40 ldr x1, [x1, #24] → blr x1 4.20 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] 0.70 ldr x0, [x1, #8] 0.70 ldr x1, [x1, #24] 0.70 → blr x1 0.70 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 2.10 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] ldr x1, [x1, #24] 4.20 → blr x1 stlr w0, [x22] 1.40 ldr x0, [x19, #64] add x22, x0, #0x38 2.80 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] ldr x1, [x1, #24] 1.40 → blr x1 2.10 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] 1.40 ldr x0, [x1, #8] ldr x1, [x1, #24] → blr x1 1.40 stlr w0, [x22] 0.70 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] 0.70 ldr x0, [x1, #8] ldr x1, [x1, #24] 0.70 → blr x1 1.40 stlr w0, [x22] 1.40 ldr x0, [x19, #64] add x22, x0, #0x38 0.70 ldr x1, [x19, #56] ldr x0, [x1, #8] ldr x1, [x1, #24] 3.50 → blr x1 2.10 stlr w0, [x22] add x21, x21, #0x1 cmp x21, x20 ↑ b.lt 24 1e8: ldp x21, x22, [sp, #32] ldp x19, x20, [sp, #16] ldp x29, x30, [sp], #48 ← ret